Demand for a non-volatile memory device that maintains the stored state of information even when power is interrupted has been increased. As an example of the non-volatile memory device, a flash memory device in which memory cells are connected as a NAND string by sharing junctions is widely used to store massive information. As increase in memory capacity of the NAND flash memory device is required, decrease in size of a cell transistor that forms the memory cell has been largely required and increase in integration degree by this decrease in size of a cell transistor is also required.
In order to realize a smaller sized cell transistor, decrease in critical dimension size of a gate of the transistor is required. However, the decrease in critical dimension size has been limited by limitation in exposing resolution for pattern transcription. Also, as the size of the cell gate is decreased to tens nm, for example to less than 40 nm, cell current is rapidly reduced and this causes deterioration in operation properties of the transistor. Such limitation in exposing resolution or reduction in cell current limits decrease in memory cell size and consequently limits increase in integration degree of a memory device.
In order to overcome the limitation in integration degree of a memory device, trials for stacking cell transistors in a direction perpendicular to a substrate has been suggested instead of realizing planar cell transistors. In consideration of the limitation in integration of planar transistors into a limited substrate area, the stacking of transistors in a direction perpendicular to a substrate will overcome this limitation to the planar area. Therefore, in order to realize a memory device with higher integration degree, it may be considered a solution in that cell transistors are stacked in a direction perpendicular to a substrate and the stacked transistors are electrically connected with one another to constitute NAND strings.